`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:32:15 03/24/2009 
// Design Name: 
// Module Name:    controller 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module controller(ibus,clk,Aselect,Bselect,dselect,imm,sint,cint,memtoreg,memread,slt,sle);

input [31:0] ibus;

output [31:0] Aselect, Bselect,dselect;

input clk;

output imm, cint,memtoreg,memread,slt,sle;

output [3:0]sint;
reg memtoreg,memread,slt,sle;



wire [31:0] wire1,wire2;

wire [3:0] sint;



decoder5X32 rs(
.in(ibus[25:21]),
.out(Aselect)
);


decoder5X32 rt(
.in(ibus[20:16]),
.out(wire1)
);



assign Bselect = wire1;

decoder5X32 rd(
.in(ibus[15:11]),
.out(wire2)
);




mux2X1 mux1(
.in1(wire1),
.in2(wire2),
.sel(imm),
.out(dselect)
);


opdecoder opcodedecoder(
.opcode(ibus[31:26]),
.func(ibus[5:0]),
.imm(imm),
.s(sint),
.cin(cint)
);

always @ (ibus)
begin
if(ibus[31:26] == 6'b011110)
memread = 1;
else
memread = 0;
end

always @ (ibus)
begin
if(ibus[31:26] == 6'b011111)
memtoreg = 1;
else
memtoreg = 0;
end

always @ (ibus)
begin
if( (ibus[31:26] == 6'b000000)&& (ibus[5:0] == 6'b110110) )
slt = 1;
else
slt = 0;
end

always @ (ibus)
begin
if(  (ibus[31:26] == 6'b000000)&& (ibus[5:0] == 6'b110111)  )
sle = 1;
else
sle = 0;
end


endmodule
